Open source FPGA silicon in the wild, and it works.

> slighly crazy

What a lovely euphemism.

Signed: someone slightly crazy.

I wonder if they will be inviting him to the next RISC-V design committee meeting.

For a friendly meeting, like Julius Caesar had on March 15, 44 BC.

"This time its different".

Spot on, while reading this post I couldn't help be wonder "but what about the prototypes"?

No AI was used either for the project itself or for the post. I encourage you to look at the code and the git history.

As the designer of "an ethernet connected beacon that counts and never overflows until the heat death of the universe" (https://talesonthewire.com/projects/until_heat_death_do_us_p...) I believe you have found the perfect audience for a memeish hardware project. So don't expect anything but my upmost support. :)

I detailed the roadmap for custom ASIC design a bit here: https://talesonthewire.com/projects/two_weeks_until_tapeout/... and joining the Tiny Tapeout discord community is a great place to reach out for help.

> So for everyone else also running multiple instances of experimental hardware on their local network I have added an additional 2 Byte magic number using the all so original 0xCAFE (little endian) allowing packet parsers to distinguish between this ASIC’s experimental traffic and your other experimental traffic.

Just saying, it's good form to do network stuff in big endian. Although since it's already done I dunno how hard you should work to retcon that to 0xFECA...

If your 0xCAFE gives you a 0xFECA1A55, stop going there...

Last time I eat vegetables..

Thanks for the pointers, hopefully I get some time to get started in that project soon!

Although I should point out that you missed the opportunity tor making the world's slowest counter and avoiding needing any expensive memory. Just declock it to an extreme degree. Hard to debug a design that never outputs anything for literal eons though.

You could easily drop the clock to 32kHz but that only saves 10 bits out of nearly 400. Getting to 1Hz requires increasing amounts of analog circuitry and only saves 26 bits. Going many powers of 2 slower starts to require counters inside your clock, so now you're replacing expensive integrated bits with much more expensive discrete logic bits.

So, since clocking low can't save you many bits, might as well give it enough bits to handle any clock up to the limits of your transistors.

No AI was used either for the project itself or for the post.

True, I went over the EDA stack a bit in a previous article here: https://talesonthewire.com/projects/blake2s_hashing_accelera...

This used the librelane classic flow, so it's a lot of verilator, yosys, openroad, opensta, magic and klayout. :)

You can join multiple Tiny Tapeout tiles (grid squares) together to form bigger projects, which is what I did here. It's actually one of the bigger 4 grid projects.

Also how much you can fit really depends on the node the shuttle is targeting. So I was in luck that this was on Global Foundries 180nm as you can cram in a lot for flip-flops onto a single tile compared with Skywater 130nm. On the other hand the gates are much slower than on Skywater 130nm.

Hopefully both programs will be around for a while, so if you are still interested when you have more time you can join the shuttle then.

You can check out the tiles for this project and their exact location on the TT chip[0].

[0] https://tinytapeout.com/chips/ttgf26b/tt_um_coffeepot

Nice, thanks for posting the link. For the people unfamiliar with the Tiny Tapeout program: everyone that gets a copy of the Tiny Tapeout chip will be getting a copy of all the ASICs on the shuttle.

Sounds like they could have used you on that team. Bad luck, but it at least you can walk away proud knowing it was not an issue with your technical skills. :)