MyHDL parses a normal Python AST and translates it to Verilog statements. In the end, you seem to end up with the exactly same abstraction layer as Verilog/VHDL, just with a Python syntax. There is a very limited subset of advanced Python composability constructs you can use without hitting a limitation of the AST walker and translator. And when you do hit it, it's fairly annoying to debug. In the end, I don't see it's use over writing straight Verilog/VHDL, apart from it being easier to test.

Migen, on the other hand, is a system where you write native Python code that doesn't pretend to be then running on the FPGA. Instead, your code stitches together an RTL AST, which can then be either simulated or converted to Verilog. Your Python code is effectively a RTL logic generator (AFAIK this is exactly how Chisel/SpinalHDL work, too). You can then compose these low-level constructs into higher layer abstractions- for instance, the stock Migen framework comes with an FSM abstractions, which takes care of all the boilerplate if declaring state machines (state register and values, separate synchronous/combinatorial logic statements, etc.). It also comes with abstractions for Arrays, (B)RAM, FIFOs, priority encoders...

Finally, Migen is the base of the MiSoC project, which abstracts away enough digital logic to let you connect, in Python, high-level constructs like buses, CPUs, DRAM controllers, etc. in order to dynamically construct a system-on-chip.