> The fact that Intel's only new releases on 10nm are <=6 core low power products suggests their yields are still poor.
That logic seems backwards. If you have poor yields you tend to favor higher-margin products (i.e. datacenter CPUs). This is a laptop CPU intended to sell at significantly lower $/mm2.
As far as chiplets: multichip packages are an ancient idea, and the industry goes back and forth on them. Both Intel and AMD shippsed multi-chip solutions way back in the day, the current age of integration is actually the anomaly. You win on yield but lose on package costs, and the decision as to which to use depends on the specifics of the market you're trying to target.
Certainly AMD would prefer to ship single-chip solutions and pocket the savings, but they can't. Likewise Intel accepts some loss of scaling because of the need to share die designs across the product line.
The issue is your defect rate for larger chips. If a small laptop CPU only has 25% of chips being fully functional, a 4x the size server chip will only yield 0.39% of chips being defect free.
I say this having no idea what Intel's defect rate is right now, and I acknowledge fusing of bad sections can mitigate this a bit.
Laptops (and for that matter mobile SoCs) are smaller, so higher defect rates can be tolerated as you can still get reasonable yields. you need a mature process to manufacture large chips (economically).
That logic seems backwards. If you have poor yields you tend to favor higher-margin products (i.e. datacenter CPUs). This is a laptop CPU intended to sell at significantly lower $/mm2.
As far as chiplets: multichip packages are an ancient idea, and the industry goes back and forth on them. Both Intel and AMD shippsed multi-chip solutions way back in the day, the current age of integration is actually the anomaly. You win on yield but lose on package costs, and the decision as to which to use depends on the specifics of the market you're trying to target.
Certainly AMD would prefer to ship single-chip solutions and pocket the savings, but they can't. Likewise Intel accepts some loss of scaling because of the need to share die designs across the product line.