The article says that Apple isn't making full use of the 5nm process node, and blames lack of SRAM scaling for it (presumably due to the large amount of L3 cache). Is this a problem that all processors are about to hit, or is this going to be overcome once process engineers are more familiar with 5nm?
This bit didn't make a lot of sense to me. SRAM is routinely the MOST optimized and MOST worried-over aspect of silicon layout. SRAM cell architectures get hand-optimized carefully years in advance of any process improvements. They aren't just logic that gets spit out of generic tooling.
So while it would make sense that a new process would have new design rule that didn't map well to older EDA tooling, it's harder to see that argument holding for SRAM. If SRAM isn't scaling, why is general logic?
> It can be noted that the cell size reduction rate from 2017 to 2018 to 2019 is much slower than the rate for preceding years 2011 to 2017, showing that SRAM cells have not been scaling at the same rate as logic in general. At IEDM 2019, the 5nm process was quoted to have 1.84x logic density improvement compared to 1.35x SRAM density improvement[1]
0.021um per cell [1] for TSMC N5 vs 0.027um per cell [0] for TSMC N7.
Even if Apple did everything right, they'd still be behind due to the limits of the process.
It's not uncommon for different components to scale differently.
They're often literally made out of different metals that have different resistance characteristics at different wire gauges, for example.
Interconnects was a very famous case, but many aspects of electrical engineering change when you get that small, because hey if you shrink the diameter of a wire by half guess what happens to the volume.
Semiconductor engineering is the field of dealing with a thousand of these tiny problems, and an improvement in the photolithography wavelengths is actually an abstraction of solving the thousands of tiny problems involved with all the different materials.
They optimize SRAM far in advance of introducing the process, after all this is one of the most critical components. It's very unlikely you'll see any further SRAM improvement on this process, but a process optimization can improve it (and everything else).
