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These things aren't _really_ two-dimensional. They're not really three-dimensional either, but they are objects built out of layers of two-dimensional things. When you measure number of transistors per unit area you will inevitably see something more dense than the "number of 5nm square in a millimeter of area".

It's the silicon equivalent of measuring one's BMI.



Video games used to call their pseudo-3d display 2.5D, or if they were feeling fancy, isomorphic.

There is a little freedom in the Z axis, but not very much. But if speed of light matters to performance, then a chip design that increases the z axis decreases the euclidean distance between any two gates, which should (or at least could) matter to performance, right?


> But if speed of light matters to performance

It barely matters. Gate delays and thermal limits outweigh distance by a huge factor. If you need to go further distances then you can wait one cycle and cover a relatively huge length.


> you can wait one cycle and cover a relatively huge length.

At the cost of increasing pipeline depth, right? We've been wrestling with that forever.


I would expect your pipeline steps to be far smaller than this scale.

We've been wrestling with the number of pipeline stages vs. the number of transistors in the critical path forever. Not so much physical distance.


Ultimately it depends on the design but you're basically right, yes.




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