AFAIK: Apple Silicon features an MSR you can toggle which swaps the memory model for a core between ARM's relaxed model and x86's TSO model, all at once. When Rosetta2 launches an app, and translates it, it simply tells the kernel that the process, when given an active slice of CPU time, should use the TSO memory model, not the relaxed one. Only Rosetta2 can request this feature. That's about all there is to it, and it does this whether the app is multicore or not (yes TSO is only needed in multicore, but enabling it unilaterally is simpler and has no downsides for emulating single-core x86 apps.)
There's also a similar MSR for 4k vs 16k page sizes I think, another x86 vs Apple Silicon discrepancy, but I'm not sure if Rosetta2 uses that, too.
I think I understand now. Rosetta is just doing translation from x86 to ARM; however, native ARM doesn't have a notion of TSO which means they're still putting in the logic to maintain TSO just to assist with the better emulation performance. On a purely ARM machine I guess that logic wouldn't be needed.
There's also a similar MSR for 4k vs 16k page sizes I think, another x86 vs Apple Silicon discrepancy, but I'm not sure if Rosetta2 uses that, too.