Yes, but single-stage conversion from 48 V to ~1.2 V core/memory voltages is inefficient with the typical buck topology, due to the low duty cycle.
There are solutions based on ZCS (+ZVS) (semi-)resonant switched capacitor topologies that could (technically) do this in essentially one stage. But because they are still somewhat recent and rely on either GaN enhancement-type FETs or low-average-blocking-voltage topologies that make use of e.g. small 5V-capable IC process nodes and some tricks to have the individual power transistors floating.
There are solutions based on ZCS (+ZVS) (semi-)resonant switched capacitor topologies that could (technically) do this in essentially one stage. But because they are still somewhat recent and rely on either GaN enhancement-type FETs or low-average-blocking-voltage topologies that make use of e.g. small 5V-capable IC process nodes and some tricks to have the individual power transistors floating.