That’s also a problem. I had high hopes for ‘free’ RISC-V alternatives while not really being a fan of the ISA, but Intel’s ‘foundary innovation’ chiplet program is totally unacceptable - because it keeps a company I simply don’t trust (ME) controlling the root of trust in silicon where the most desirable quality is the absence of exactly that. I may end up using Ampere chips in spite of a distaste of ARM. I’m also seriously pursuing an OpenSPARC based SoC, with a test design through Skywater. At the latest process node SPARC V9 is plenty competitive and there’s a clear market for a high core count SoC absent of additional IP. I just need a modern memory controller. I’m going to document the process at silicon.engineering although that site is just a placeholder now.