This looks like a curious case, non-fixed-length vectorization code in RISC-V:
> "Perhaps the most interesting part of the open RISC-V instruction set architecture (ISA) is the vector extension (RISC-V "V"). In contrast to the average single-instruction multipe-data (SIMD) instruction set, RISC-V vector instructions are vector length agnostic (VLA). Thus, a RISC-V "V" CPU is flexible in choosing a vector register size while RISC-V "V" binary code is portable between different CPU implementations."
Classical vector machines (think Cray) had flexible vector sizes. But eventually they were buried under a tide of consumer processors, which were fundamentally scalar. Then as these machines took over the world, they had to go into every niche, so the MMX style “fixed length vector instruction” was invented, for CPUs that might have to do some math while still fitting into that paradigm.
RISC-V also has the P extension, which follows this pattern. It will be very cool if RISC-V proves flexible enough to really enable a resurgence of classic vectors though.
No, classic Cray did have a fixed vector size (4096 bits, or 64 double precision floating point values) both in the HW and the ISA. What it did have, however, which most contemporary SIMD ISA's lack, was a vector length register which allowed masking the end of the vector register. That meant the compiler didn't have to generate a scalar loop tail to handle the final iterations of a vectorized loop, it just set the vector length register to mask of the end of the vector data register, which meant that load/store/arithmetic instructions only worked on the first N elements in the vector rather than the full 64.
I think the RISC-V V extension, as well as ARM SVE, both have something similar as well. What RVV and SVE have, that Cray vector ISA didn't, is the ability to support different HW vector register lengths with the same ISA.
> "Perhaps the most interesting part of the open RISC-V instruction set architecture (ISA) is the vector extension (RISC-V "V"). In contrast to the average single-instruction multipe-data (SIMD) instruction set, RISC-V vector instructions are vector length agnostic (VLA). Thus, a RISC-V "V" CPU is flexible in choosing a vector register size while RISC-V "V" binary code is portable between different CPU implementations."
https://gms.tf/riscv-vector.html