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AMD and Intel are both making quad channel APUs akin to the M2 Pro.

https://videocardz.com/newz/intel-arrow-lake-p-with-320eu-gp...

(Sorry, I cannot find the AMD rumor link atm)

But TBH the hybrid design is less interesting than you think, just because nothing really takes advantage of it. Hence Intel canceled their datacenter APU in favor of a pure Falcon Shores GPU due to a lack of interest from customers.



AMD halo strix is the future APU with a 256 bit wide interface. Boggles my mind with a multi-year GPU shortage that AMD didn't bring a wider memory interface to iGPUs. Obviously they can do it since the ps5 and Xbox X have been shopping for some time.

Looks like someone ported llama to apples metal v3 already and are getting 5 tok/s on a 65b model.


AMD should have re-used the Xbox APU, but other than that it makes no economic sense?

The tape out cost would be huge, the die would be huge. Either the mobo/socket would be super expensive and niche, or consumers would be pissed about non expandable RAM.

Laptop OEMs didn't even want the Steam Deck chip or Broadwell-edram back then, much less a big expensive APU.


AMD has the pieces, they ship a Xbox version, PS5 version, the sTRX4 socket for the threadripper, and for any of their chiplet products the IOD would be the only changed piece of silicon. Any updates could be amortized over their pending threadripper upgrades (4 channel), sienna products (6 channel), or threadripper pro (8 channel).

Much like how Apple sells 128 bit wide (mini and mba), 256 bit wide (m1/m2 pro), 512 bit wide (m1/m2 max), and 1024 bit wide (m1/m2 ultra).

I think the desktop/laptop vendors would have jumped at a nice iGPU/APU when they couldn't get normal GPUs.

Obviously AMD agrees, they shipped the PS5/XboxX and have a 256 bit wide APU planned for 2024. Just way later than I had hoped.


The big reason why parallel memory buses aren’t wider is pin count. If you have all the memory interfaces over the substrate, the bus can be as wide as the substrate can accommodate.

BTW, what is the usual width of memory buses in discrete GPUs?


It boggles my mind that apple can do 128 bit, 256 bit, and 512 bit wide memory interfaces on thin/light laptops that are price competitive with PC laptops in the same segment while having excellent battery life.

In the previous gen even a relatively low end card like the 3060 Ti has a 256 bit wide memory interface. In the current generation the 4070 (which is a higher in the product stack) is 192 bits. The RTX 3080 (prev gen) is 320 bits wide the 4080 (current gen) is 256 bits.

Generally the trend is more cache, less width, and less bandwidth. Which is great ... for things that are cache friendly, but not everything is.


> just because nothing really takes advantage of it.

This is precisely why AMD, Intel, and Nvidia should think about making workstation-class machines with the lowest end of these - because until more people have one to play with, there won't be much to do with them.


There were rumors of an AMD one... That also never materialized.

Its a chicken and egg problem, I think. A big APU is so expensive that it doesn't really make sense without a very specific workload (like in a console), and the workloads dont really appear without the APUs.




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