AFAIK, creating latches is just as easy in Verilog as in VHDL. They use the same... | Hacker News

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		tverbeure 15 days ago \| parent \| context \| favorite \| on: VHDL's Crown Jewel AFAIK, creating latches is just as easy in Verilog as in VHDL. They use the same model to determine when to create one. But with a solid design flow (which should include linting tools like Spyglass for both VHDL and Verilog), it’s not a major concern.

nickelpro 14 days ago [–]

SystemVerilog basically fixes this with always_comb vs always_latch.

There's no major implementation which doesn't handle warning or even failing the flow on accidental latch logic inside an always_comb.

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