The FPU here has 5,000 transistors.

If you can stomach the lack of full IEEE compliance, you can build a full 32-bit FPU with ~100,000 transistors:

http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.71....

So really what we have here is at best a ~20x performance boost in exchange for an absolute programming nightmare.

Or you can switch to DSP-like fixed point math with ~25K transistors per ALU:

http://www.idosi.org/wasj/wasj2%284%29/12.pdf

So now we're down to ~5x better performance in exchange for that programming nightmare.

And just to be thorough, if you're hellbent on nontraditional arithmetic, here's an error-free 32-bit integer ALU made with 1696 transistors, that would be >3x more efficient than the architecture here (assuming all you care about is throughput):

http://www.iosrjournals.org/iosr-jece/papers/Vol3-Issue6/B03...

So now we're talking at best 1/3 to 1/4 the performance of what they could get if they dropped logarithmic math and went to something more predictable. Someone call Vinod Khosla, we're gonna be rrrriccchhhh...