- HDL code doesn't have variables the way programming code does. Sure, you can store state in latches (and other more roundabout ways), but a good design tries to avoid this.
- You can have "functions" that take parameters, but what you're really doing is instantiating blocks of hardware according to said parameters.
- Instead of variables to functions, what you really care about is signals as input and output to hardware blocks. (and ultimately at the final hardware implementation, propagation time and power of said signals. Especially the clock. OMG the clock...)
Honestly, I found VHDL made complete sense from approaching it after drawing digital circuit diagrams, as the description code mapped pretty clearly to that. Approaching it from an "imperative programming" background makes little sense, and saying it's "concurrent programming" just ends up confusing the issue more, IMHO.
Absolutely agree with learning digital circuit design first. Before writing a single line of HDL, you should know exactly what you want to be synthesized.
Unfortunately all to many courses approach like learning a new programming language. To me this is like teaching CAD before teaching how to draw a rectangle.
It's more like wiring together a series of tubes. The signal has to propagate from one end of the tubes to the other in a single clock cycle. Note that the tubes can go backwards, so you can feed the output of the tube into the next input of itself. Hardware programming like this is actually extremely fun, but for some reason the widely available languages for doing it suck. And make what is going on in the hardware opaque and difficult to understand for any non trivial applications. (We're talking 100000s of lines of code to do anything nontrivial).
I think you could. Contrary to most comments on this page, I do think that you should be able to write high-level code with "if" and "while" and have the compiler generate the hardware for you. Actually, that's what we (Synflow) are doing with our language. So you don't have to spend so much time learning Verilog/VHDL and typing all those Finite State Machines and scheduling next state processes and so on. Take a look at our website www.synflow.com and let us know what you think!
